The present invention relates to a test facilitation circuit built into a memory device such as a dynamic random-access memory.
A dynamic random-access memory (DRAM) is tested by writing various test data patterns into its memory-cell array, then reading the written data. A test facilitation circuit speeds up the testing process by providing a high-speed synchronous interface between the memory device and external test equipment, and an auxiliary memory circuit for temporary storage of the test data within the memory device. The auxiliary memory circuit has a capacity equal to, for example, one row of memory cells in the memory-cell array.
In a conventional test facilitation circuit, test data are transferred into the auxiliary memory circuit until the auxiliary memory circuit is full, then written all at once into the memory-cell array. To write a test pattern into the memory-cell array, this two-step process is repeated for every row of memory cells, for example, so despite the high-speed synchronous interface, much time is consumed in the transfer of data from the test equipment to the auxiliary memory circuit. Further details will be given below.